Multi-rate DEM with mismatch noise cancellation for digitally-controlled oscillators

ABSTRACT

A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

PRIORITY CLAIM AND REFERENCE TO RELATED APPLICATION

The application claims priority under 35 U.S.C. § 119 and all applicablestatutes and treaties from prior provisional application Ser. No.62/722,276, which was filed Aug. 24, 2018, and is incorporated byreference herein.

STATEMENT OF GOVERNMENT INTEREST

This invention was made with government support under grant number1617545 awarded by National Science Foundation. The government hascertain rights in the invention.

FIELD

A field of the invention is frequency synthesis. Example applications ofthe invention are in clock generation, in wired and in wirelesscommunications. A particular application of the invention is in wirelesstransceivers for the generation of radio frequency (RF) local oscillatorsignals used to up-convert and down-convert transmitted and received RFsignals.

LIST OF ABBREVIATIONS

The following abbreviations are used in the description and are providedhere for ease of reference.

CMOS Complementary Metal Oxide Semiconductor

DCO Digitally Controlled Oscillator

DEM Dynamic Element Matching

DLF Digital Loop Filter

FCE Frequency Control Element

IC Integrated Circuit

LC-Based Inductor-Capacitor Based

MNC Mismatch-Noise Cancellation

PEDC Phase-error-to-digital converter

PLL Phase Locked Loop

PSD Power Spectral Density

RF Radio Frequency

SB Digital Switching Block

BACKGROUND

Evolving wireless communication standards place increasingly stringentperformance requirements on the frequency synthesizers that generate RFlocal oscillator signals for up and down conversion in wirelesstransceivers. Conventional analog fractional-N PLLs with digitaldelta-sigma (As) modulation are the current standard for such frequencysynthesizers because of their excellent noise and spurious toneperformance. See, e.g., T. A. Riley, M. A. Copeland, T. A. Kwasniewski,“Delta-sigma modulation in fractional-N frequency synthesis,” IEEEJournal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993.Unfortunately, they require high-performance analog charge pumps andlarge-area analog filters, so the trends of CMOS technology scaling andincreasingly dense system-on-chip integration have created aninhospitable environment for them.

Digital fractional-N PLLs have been developed over the last decade toaddress this problem. See, e.g., C. Hsu, M. Z. Straayer, M. H. Perrott,“A Low-Noise, Wide-BW 3.6 GHz Digital ΔΣ Fractional-N FrequencySynthesizer with a Noise-Shaping Time-to-Digital Converter andQuantization Noise Cancellation,” IEEE International Solid-StateCircuits Conference, pp. 340-341, February 2008. They avoid large analogloop filters and can tolerate device leakage and low supply voltageswhich makes them better-suited to highly-scaled CMOS technology thananalog PLLs. They are increasingly used in place of analog PLLs asfrequency synthesizers. To date, analog PLLs have the best phase errorperformance, but digital PLLs have the lowest circuit area and are morecompatible with highly-scaled CMOS IC technology. Thus, reducing phaseerror in digital PLLs has been the subject of intensive research anddevelopment for over a decade.

A continuing problem in digital PLLs concerns frequency control element(FCE) mismatches. Such FCE mismatches remain a significant source ofphase error in high-performance digital PLLs. See, C. Weltin-Wu, E.Familier, and I. Galton, “A linearized model for the design offractional-N digital PLLs based on dual-mode ring oscillator FDCs,”IEEETrans.Circuits Syst. I, Reg.Papers, vol. 62, no. 8, pp. 2013-2023,August 2015. Prior attempts to address the FCE mismatch problem use anoffline calibration technique that requires several minutes to complete.See, O. Eliezer, B. Staszewski, J. Mehta, F. Jabbar, and I. Bashir,“Accurate self-characterization of mismatches in a capacitor array of adigitally-controlled oscillator,” in Proc. IEEE Dallas Circuits Syst.Workshop, October 2010, pp. 17-18; O. Eliezer, B. Staszewski, and S.Vemulapalli, “Digitally controlled oscillator in a 65 nm GSM/EDGEtransceiver with built-in compensation for capacitor mismatches,” inProc. IEEE Radio Freq. Integr. Circuits Symp., June 2011, pp. 5-7.

A digitally controlled oscillator (DCO) is an oscillator whose frequencyis controlled by one or more FCEs, each of which is controlled by a1-bit digital sequence. For instance, each FCE in an LC-based DCOcontributes to the DCO's tank a capacitance that takes on one of twovalues depending on the state of the FCE's input bit. Changing the FCE'sinput bit increases or decreases the DCO frequency by a fixed frequencystep.

The instantaneous frequency of a DCO is given by a fixed offsetfrequency plus f_(tune)(t), where:

$\begin{matrix}{{{f_{tune}(t)} = {\sum\limits_{i = 1}^{N_{FCE}}{f_{i}(t)}}},} & (1)\end{matrix}$

N_(FCE) is the number of FCEs in the DCO, and f_(i)(t) is thecontribution of the ith FCE to the DCO frequency. Ideally,f _(i)(t)=(b _(i) [m _(t)]−½)Δ_(i),  (2)where b_(i)[m] is the FCE's input bit value (either 0 or 1) over the mthclock interval, m_(t)=└f_(FCE)t┘, f_(FCE) is the clock-rate of the inputbit, and Δ_(i) is the FCE's frequency step size.

The DCO's input sequence, d[n], represents the ideal value off_(tune)(t) over the nth clock interval. For example, suppose d[n] isrepresented as a 16-bit two's complement code where the leastsignificant bit (LSB) represents a DCO frequency step of Δ (e.g., Δ=100Hz). Then

$\begin{matrix}{{{d\lbrack n\rbrack} = {( {{{- 2^{15}}{d_{15}\lbrack n\rbrack}} + {\sum\limits_{i = 0}^{14}{2^{i}{d_{i}\lbrack n\rbrack}}}} )\Delta}},} & (3)\end{matrix}$where d_(i)[n], for each i=0, 1, . . . , 15, is the value of the ith bitof the code (either 0 or 1) over the nth clock interval.

Ideally, f_(tune)(t)=d[n_(t)], where n_(t)=└f_(in)t┘ and f_(in) is theclock-rate of the DCO input. Equations (1)-(3) with f_(FCE)=f_(in) implythat this can be achieved with a bank of 16 FCEs, where the ith FCE'sfrequency step size is Δ_(i)=2^(i−1)Δ, b_(i)[n]=d_(i−1)[n] for i=1, 2, .. . , 15, and b₁₆[n]=1−d₁₅[n].

Unfortunately, in PLL applications that require low phase noise, such aslocal oscillator synthesis for cellular telephone transceivers, DCOswith minimum frequency steps of tens of Hz are required, but mostexisting FCEs have minimum frequency steps of tens of kHz or more. Acommon solution to this problem is described next for an example case inwhich f_(tune)(t) needs to be controlled in steps of Δ, yet the smallestrealizable FCE frequency step size is Δ_(min)=2⁸Δ. In this case, the 8LSBs of d[n] are said to represent the fractional part of d[n] becausethey cause DCO frequency steps that are fractions of Δ_(min), and the 8most significant bits (MSBs) of d[n] are said to represent the integerpart of d[n] because they cause DCO frequency steps that are multiplesof Δ_(min).

The basic approach utilizes two FCE banks: an integer FCE bankcontrolled by the integer part of d[n], and a fractional FCE bankcontrolled by the output of an oversampling digital ΔΣ modulator drivenby the fractional part of d[n]. The ΔΣ modulator's highpass-shapedquantization noise is lowpass filtered by the DCO, so provided theoversampling rate is sufficiently high, it negligibly contributes to theDCO's phase error.

FIG. 1 shows a specific example in the context of an LC-based DCO, wherep_(t)=└f_(fast)t┘, f_(fast)>>f_(it), and d_(I)[n_(t)] and d_(F)[n_(t)]are the integer and fractional parts of d[n_(t)], respectively. Thef_(fast)-clk signal is such that p_(t) changes synchronously with n_(t),so that n_(t) can be written as a function of p_(t), i.e.,n _(t) =g(p _(t)).  (4)

In this example g(p_(t))=└(f_(in)/f_(fast))p_(t)┘, where f_(fast)/f_(in)is an integer much greater than 1.

It follows from (3) that d[n_(t)]=d_(I)[n_(t)]+d_(F)[n_(t)], where

$\begin{matrix}{{d_{I}\lbrack n_{t} \rbrack} = {( {{{- 2^{15}}{d_{15}\lbrack n_{t} \rbrack}} + {\sum\limits_{i = 8}^{14}{2^{i}{d_{i}\lbrack n_{t} \rbrack}}}} )\Delta}} & (5) \\{and} & \; \\{{d_{F}\lbrack n_{t} \rbrack} = {\Delta{\sum\limits_{i = 0}^{7}{2^{i}{{d_{i}\lbrack n_{t} \rbrack}.}}}}} & (6)\end{matrix}$

As shown in FIG. 1, d_(F)[n_(t)] is sampled at a rate of f_(fast) by asecond-order digital ΔΣ modulator. The ΔΣ modulator's output is afour-level sequence quantized to multiples of Δ_(min) and can be writtenasy _(ΔΣ) [p _(t) ]=d _(F) [n _(t) ]+e _(ΔΣ) [p _(t)],  (7)where e_(ΔΣ)[p_(t)] is second-order highpass-shaped quantization noiseplus any dither used within the ΔΣ modulator. A thermometer encoder mapsy_(ΔΣ)[p_(t)] to a 4-bit thermometer code which drives a bank of fourFCEs, each with a frequency step of Δ_(min). It follows from (1), (2)and (7) that the contribution of the fractional FCE bank to the DCOfrequency, f_(F)(t), is

$\begin{matrix}{{f_{F}(t)} = {{\sum\limits_{i = 1}^{4}{f_{i}(t)}} = {{d_{F}\lbrack n_{t\;} \rbrack} + {{e_{\Delta\Sigma}\lbrack p_{t} \rbrack}.}}}} & (8)\end{matrix}$

The integer FCE bank is directly driven by d_(I)[n_(t)]. Specifically,the ith FCE, for i=5, 6, . . . , 11, has inputb_(i)[n_(t)]=d_(i+3)[n_(t)] and frequency step size Δ_(i)=2^(i+3)Δ, andthe 12th FCE has input b₁₂[n_(t)]=1−d₁₅[n_(t)] and frequency step sizeΔ₁₂=2¹⁵Δ. It follows from (1), (2) and (5) that the contribution of theinteger FCE bank to the DCO frequency, f_(I)(t), is

$\begin{matrix}{{{f_{I}(t)} = {{\sum\limits_{i = 5}^{12}{f_{i}(t)}} = {d_{I}\lbrack n_{t} \rbrack}}},} & (9)\end{matrix}$where a constant additive term has been omitted.

The contribution of the two FCE banks to the DCO frequency isf_(tune)(t)=f_(I)(t)+f_(F)(t), so (8) and (9) imply thatf _(tune)(t)=d[_(t)]+e _(ΔΣ)[p _(t)].  (10)

Accordingly, e_(ΔΣ)[p_(t)] causes DCO frequency error. The DCO's phaseerror is the integral of its frequency error, so as mentioned above, alowpass-filtered version of e_(ΔΣ)[p_(t)] appears as a component of theDCO's phase error. Given that e_(ΔΣ)[p_(t)] has a highpass-shapedspectrum that peaks at f_(fast)/2, its contribution to the DCO's phaseerror can be made negligible relative to other sources of phase error iff_(fast) is large enough.

The analysis above presumes that the FCEs are ideal. Unfortunately,non-ideal circuit behavior causes f_(i)(t) to deviate from (2). Forexample, suppose for now that f_(i)(t) is modeled as ideal except for astatic gain error given by α_(i), i.e.f _(i)(t)=(b _(i)[m _(t)]−½)α_(i)Δ_(i).  (11)

Ideally, α_(i)=1 for i=1, 2, . . . , N_(FCE), but inevitable componentmismatches introduced during fabrication cause α_(i) to deviate from 1.

Repeating the analysis for the example in FIG. 1 with (11) in place of(2) givesf _(tune)(t)=α_(F) f _(tune-ideal)(t)+e _(F)(t)+e _(I)(t)+(α_(I)−α_(F))d_(I)[n _(t)],   (12)where f_(tune-ideal)(t) is given by the right side of (10), α_(F) andα_(I) are the averages of α_(i) for i=1, 2, 3, 4 and i=5, 6, . . . , 12,respectively,

$\begin{matrix}{{e_{F}(t)} = {\sum\limits_{i = 1}^{4}{( {\alpha_{i} - \alpha_{F}} )( {{b_{i}\lbrack p_{t} \rbrack} - {1\text{/}2}} )\Delta_{\min}}}} & (13) \\{and} & \; \\{{e_{I}(t)} = {\sum\limits_{i = 5}^{12}{( {\alpha_{i} - \alpha_{I}} )( {{b_{i}\lbrack n_{t} \rbrack} - {1\text{/}2}} ){\Delta_{i}.}}}} & (14)\end{matrix}$where f_(tune-ideal)(t) is given by the right side of (10), α_(F) andα_(I) are the averages of α_(i) for i=1, 2, 3, 4 and i=5, 6, . . . , 12,respectively.

Hence, the FCE static gain errors introduce a gain factor, α_(F), andthree additive error terms to f_(tune)(t). The α_(F) gain factor doesnot significantly degrade performance in typical PLLs. In contrast, asexplained next, the three additive error terms in (12) tend to causespurious tones and increase phase error in PLLs because they arenonlinear functions of d[n_(t)].

The individual bits of d[n], i.e., d_(i)[n], for each i=0, 1, . . . ,15, each depend on d[n] but are restricted to values of 0 and 1. Hence,each d_(i)[n] is a nonlinear function of d[n]. Nevertheless, they can becombined as in (3) to yield d[n], which implies that multiplying d₀[n],d₁[n], . . . , d₁₄[n], and d₁₅[n] by 2⁰, 2¹, . . . , 2¹⁴, and −2¹⁵,respectively, and adding the results causes the nonlinear componentsfrom the individual bits to cancel each other. Any deviation from a setof scale factors proportional to those mentioned above prevents fullcancellation of the nonlinear components. It can be verified from (5),(13) and (14) that e_(F)(t), e_(I)(t), and (α_(I)−α_(F))d_(I)[n_(t)] areeach a function of a subset of the individual bits of d[n_(t)], so theyare nonlinear functions of d[n_(t)].

A partial solution to this problem is to replace the thermometer encoderin FIG. 1 with a mismatch-shaping DEM encoder. See, I. Galton, “WhyDynamic-Element-Matching DACs Work,” IEEE Trans. Circuits Syst. II Exp.Briefs, vol. 57, no. 2, pp. 69-74, March 2010. Doing so would causee_(F)(t) to be replaced by highpass-shaped noise that is free ofnonlinear distortion and is uncorrelated with d[n_(t)], so it would besuppressed by the DCO 102 like the ΔΣ quantization noise. Similarly, theinteger FCE bank 104 could be modified to accommodate a mismatch-shapingDEM encoder clocked at a rate of f_(in), which would cause e_(I)(t) tobe replaced by shaped noise that is free of nonlinear distortion and isuncorrelated with d[n_(t)]. However, f_(in □) f_(fast), less of theshaped noise would be suppressed by the DCO 102. Unfortunately, DEM asdescribed above would not help prevent the last term in (12) fromintroducing nonlinear distortion because d_(I)[n_(t)] is a non-linearfunction of d[n_(t)].

The last two terms in (12) increase the phase error in a PLL unlessd_(I)[n_(t)] remains constant once the PLL is locked. See, C. Weltin-Wu,G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer UsingRing-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,”IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015.In most published digital PLLs d[n] varies by much less than Δ_(min)when the PLL is locked, and measured results are usually presented forPLL frequencies at which can d_(I)[n_(t)] does not change during themeasurement interval. This renders the last two terms in (12) constant,so they do not contribute phase error. Unfortunately, this is not aviable option in practice because DCO center frequency drift caused byflicker noise, voltage and temperature variations, and pulling fromexternal interference cause d[n_(t)] to vary by far more than Δ_(min)over time. For instance, measurement results indicate that the frequencyof the DCO presented in [C. Weltin-Wu, G. Zhao, and I. Galton, “AHighly-Digital Frequency Synthesizer Using Ring-OscillatorFrequency-to-Digital Conversion and Noise Cancellation,” IEEEInternational Solid-State Circuits Conf., pp. 1-3, February 2015] variesby about −200 kHz/° C., which corresponds to ˜7Δ_(min) per degreeCelsius. In practice, this causes the digital PLL's phase noise toincrease drastically from time to time as d[n_(t)] slowly drifts pastinteger multiples of Δ_(min). This issue is sometimes called “spectralbreathing” because the phase noise spectrum, as viewed on laboratorymeasurement equipment, appears to swell up every now and then as if itis taking deep breaths. During these “breaths” the PLL's performance isextremely degraded. Furthermore, when the PLL is used to generate phaseor frequency modulated signals, such as a GFSK signal for a Bluetoothtransmitter, d[n_(t)] typically varies by more than Δ_(min), so thereare no periods between “breaths” during which the phase noiseperformance is good.

To address this problem, a single bank of FCEs driven by a ΔΣ modulatorand a mismatch-shaping DEM encoder could be used, where the ΔΣ modulatoroversamples d[n_(t)] instead of just d_(F)[n_(t)]. The DEM encoder wouldcause any mismatches among the FCEs to contribute shaped noise insteadof nonlinear distortion, and the oversampling would ensure that most ofthe noise is suppressed by the DCO. Unfortunately, high oversamplingratios would be required in practice, which makes this solutionimpractical because of the associated high-power consumption

SUMMARY OF THE INVENTION

A preferred embodiment is a digital fractional-N phase locked loop (PLL)with multi-rate dynamic element matching (DEM) and an adaptivemismatch-noise cancellation (MNC). The PLL includes a phase error todigital converter (PEDC) and a digital loop filter to suppressquantization noise of the PEDC and drive a digitally controlledoscillator. A digitally controlled oscillator (DCO) with a multi-rateDEM encoder includes an integer bank of frequency control elements (FCE)and a fractional bank of frequency control elements. Adaptivemismatch-noise cancellation logic operates to cancel DCO phase errorarising from frequency control element (FCE) static and dynamic mismatcherror by estimating ideal MNC coefficient values during PLL normaloperation, estimating MNC coefficient errors at each sample time, andupdating the MNC coefficient values to approach zero (FCE) static anddynamic mismatch error.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Prior Art) is a schematic diagram of a frequency controltechnique for an LC-based DC);

FIG. 2 includes a set of example waveforms related to equations (15) and(16) to provide a visual representation of the effects of FCE mismatcheson the DCO frequency;

FIG. 3 (Prior Art) is a block diagram of a mismatch-shaping segmentedDEM encoder;

FIGS. 4A-4C (Prior Art) are block (4A & 4B) and schematic (4C) diagramsshowing digital switching blocks of the FIG. 3 DEM encoder;

FIG. 5 is a block diagram of a preferred embodiment DCO with amulti-rate segmented DEM encoder that is a modification of the FIG. 3encoder;

FIG. 6 is a block diagram of a preferred slow DEM encoder used in FIG.5;

FIG. 7 is a functional diagram of a preferred embodiment second-orderdigital ΔΣ modulator used in FIG. 5;

FIG. 8 shows the fractional path of the multi-rate DEM encoder shown inFIG. 5 modified to accommodate MNC;

FIG. 9 (Prior Art) is a schematic diagram of a digital fractional-N PLLwithout MNC;

FIGS. 10A & 10B (Prior Art) respectively are a schematic diagram of asynchronization circuit used at DCO input in FIG. 9 and illustration ofthe clock signals within the DCO, p_(t), and n_(t)=g(p_(t)) forf_(fast)=4.5f_(ref);

FIGS. 11A-11C are block diagrams that illustrate a preferred digitalfractional-N PLL with the multi-rate DEM encoder and MNC;

FIG. 12 shows example frequency transients used in a simulation of theFIGS. 11A-11C digital fractional-N PLL;

FIGS. 13A-13C respectively show simulated phase noise of the FIGS.11A-11C digital fractional-N PLL; with the multi-rate DEM techniquedisabled, with the multi-rate DEM technique enabled for two cases, andwith the multi-rate DEM technique enabled and with the MNC techniquedisabled and enabled;

FIGS. 14A & 14B show the evolution of the MNC coefficient errors overtime from the simulation used to generate the curves in FIG. 13C;

FIGS. 15A & 15B show the evolution of the MNC coefficient errors overtime for 7.8·10⁷ reference periods (3 seconds) for an example case inwhich K_(a) and K_(b) are initially set to 2⁻¹ and 2⁻², respectively,and then divided by two at the times indicated by the vertical dashedlines.

DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiment methods and digital oscillators provide multi-ratedynamic element matching (DEM) and an adaptive mismatch-noisecancellation (MNC) that work together to address FCE mismatches. The DEMand the MNC run during normal PLL operation, and the MNC typicallyconverges in a few seconds from a cold start. A preferred DEM has beensimulated and succeeds in reducing noise from the FCE mismatches. TheMNC cancels DCO phase error arising from FCE mismatch error. Ideal MNCcoefficient values are estimated, during PLL normal operation, as partof the feedback loop in a digital fractional-N PLL that incorporates theDCO.

The center frequency of a conventional digitally-controlled oscillator(DCO) drifts over time due to flicker noise, voltage and temperaturevariations, and pulling from external interference. Given that the DCOfrequency is a non-linear function of the DCO's input signal, thiscauses the digital PLL's phase noise to increase drastically from timeto time because the DCO's input signal slowly drifts to counteract theDCO's center frequency drift. This issue is called spectral breathingbecause the phase noise spectrum, as viewed on laboratory measurementequipment, appears to swell up every now and then as if it is takingdeep breaths of air, during which the PLL's performance is extremelydegraded. Moreover, when the PLL is used to generate phase or frequencymodulated signals there are no periods between breaths during which thephase noise performance is good. Spectral breathing can drasticallydegrade a digital PLL's phase noise. Preferred embodiments addressspectral breathing by making the relation between the DCO frequency andits input signal linear, which is done at the expense of initiallyadding more noise to the system. However, this added noise hasproperties that can be exploited to cancel it, so that the digital PLL'sperformance is no longer degraded when the DCO's input signal changes.Overall, the price is only a slightly higher power consumption.

Preferred embodiments provide a new multi-rate DEM technique and an MNCtechnique that work together within a PLL to solve the problems thatarise from FCE mismatches are presented. As in FIG. 1, the preferredembodiment uses integer and fractional FCE banks. In the preferredembodiment, both FCE banks are driven by a multi-rate DEM encoder, whichensures that the error arising from FCE mismatches is free of nonlineardistortion. In addition, the multi-rate DEM encoder avoids high powerconsumption because most of its digital logic is clocked at a rate off_(in) instead of f_(fast). Although the hardware of preferredembodiments is different from that of the solution in which d[n_(t)] isoversampled and a DEM encoder clocked at a high rate is used to controlthe FCEs, a pessimistic power consumption analysis indicates that thepreferred techniques are at least five times more power-efficient. Muchof the additive error is not oversampled, so instead of relying on theDCO to suppress it, the MNC technique adaptively measures the error andcancels it in real time.

Preferred embodiments of the invention will now be discussed withrespect to the drawings and experiments used to demonstrate theinvention. The drawings may include schematic and/or blockrepresentations, which will be understood by artisans in view of thegeneral knowledge in the art and the description that follows.

FCEs with Δ_(i)>Δ_(min) are usually built by connecting nominallyidentical minimum-weight FCEs in parallel. Static mismatches among theseFCEs are sources of error, but other non-idealities such as thenon-instantaneous frequency transitions of realizable FCEs are alsosources of error. Hence, a more comprehensive model than (11) forf_(i)(t) isf _(i)(t)=(b _(i)[m _(t)]−½)Δ_(i) +e _(i)(t),  (15)where e_(i)(t) is error that models both the static mismatch and thenon-ideal frequency transitions of the ith FCE. b_(i)[m] is the FCE'sinput bit value (either 0 or 1) over the mth clock interval, as definedabove in (2). FCEs are designed such that frequency transitions causedby input bit changes settle within a clock period, so e_(i)(t) onlydepends on b_(i)[m_(t)−1] and b_(i)[m_(t)]. This can be modeled as

$\begin{matrix}{{e_{i}(t)} = \{ {\begin{matrix}{e_{11i},} & {{{{if}\mspace{14mu}{b_{i}\lbrack {m_{t} - 1} \rbrack}} = 1},{{b_{i}\lbrack m_{t} \rbrack} = 1},} \\{{e_{01i}(t)},} & {{{{if}\mspace{14mu}{b_{i}\lbrack {m_{t} - 1} \rbrack}} = 0},{{b_{i}\lbrack m_{t} \rbrack} = 1},} \\{e_{00i},} & {{{{if}\mspace{14mu}{b_{i}\lbrack {m_{t} - 1} \rbrack}} = 0},{{b_{i}\lbrack m_{t} \rbrack} = 0},} \\{{e_{10i}(t)},} & {{{{if}\mspace{14mu}{b_{i}\lbrack {m_{t} - 1} \rbrack}} = 1},{{b_{i}\lbrack m_{t} \rbrack} = 0}}\end{matrix},} } & (16)\end{matrix}$where e_(11i), e_(01i)(t), e_(00i), and e_(10i)(t) represent the errorover each clock interval corresponding to the four differentpossibilities of the FCE's current and prior input bit values. The FCEmodel given by (15) and (16) is analogous to that of anon-return-to-zero (NRZ) 1-bit DAC. To prevent e_(i)(t) from dependingon b_(i)[m_(t)−1], return-to-zero (RZ) FCEs could be implemented bysetting the FCEs to a signal-independent state for a fraction of eachclock period, but this is not practical for PLLs because it wouldperiodically slew the DCO frequency and thereby introduce excessivephase noise.

FIG. 2 shows example waveforms associated with (15) and (16). Aconsequence of the frequency transitions settling within a clock periodis that when an FCE's input bit does not change between clock periods,neither does its contribution to the DCO frequency, so e_(00i) ande_(11i) are constant. In contrast, e_(01i)(t) and e_(10i)(t) are notconstant because they represent deviations from the FCE's idealinstantaneous frequency transitions when its input bit changes. As shownin FIG. 2, the shape of each of these frequency transitions depends onlyon whether the corresponding FCE input changed from 0 to 1 or 1 to 0,and both e_(01i)(t) and e_(10i)(t) are 1/f_(FCE)-periodic.

Experimental results indicate, at least for the LC-based DCOs presentedin [C. Venerus and I. Galton, “A TDC-Free Mostly-Digital FDC-PLLFrequency Synthesizer with a 2.8-3.5 GHz DCO,” IEEE J. Solid-StateCircuits, vol. 50, no. 2, pp. 450-463, February 2015] and [C. Weltin-Wu,E. Familier, and I. Galton, “A Linearized Model for the Design ofFractional-N PLLs based on Dual-Mode Ring Oscillator FDCs,” IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August2015], that the frequency transition introduced by each FCE when itsinput bit changes from 0 to 1 and that when the input bit changes from 1to 0 are antisymmetric to a high degree of accuracy, i.e.,e_(11i)−e_(01i)(t)=−[e_(00i)−e_(10i)(t)]. Therefore, substituting (16)into (15), applying this observation, collecting terms and omittingconstant additive terms yields.f _(i)(t)=(b _(i)[m _(t)]−½)α_(i)(t)Δ_(i)+(b _(i)[m_(t)−1]−½)γ_(i)(t),  (17)whereα_(i)(t)=1+(e _(01i)(t)−e _(00i))/Δ_(i) and γ_(i)(t)=e _(11i) −e_(01i)(t).  (18)

Given that α_(i)(t) and γ_(i)(t) are functions of e_(01i)(t) ande_(10i)(t), which are 1/f_(FCE)-periodic, they are also1/f_(FCE)-periodic.

Multi-Rate DEM

Single-Rate Segmented DEM

Suppose the DCO's input sequence is given by (3), and for now supposethat ΔΣ quantization is not necessary because FCEs with small-enoughstep sizes are available, i.e., Δ_(min)=Δ. Even in this case, FCEmismatches are a problem because they cause nonlinear distortion. Aconventional single-rate segmented DEM encoder can be used to preventthis problem. For example, the mismatch-shaping segmented DEM encodershown in FIG. 3 can be used with 34 FCEs. See, K. L. Chan, N. Rakuljic,and I. Galton, “Segmented Dynamic Element Matching for High-ResolutionDigital-to-Analog Conversion,” IEEE Trans. Circuits Syst. I, Reg.Papers, vol. 55, no. 11, pp. 3383-3392, December 2008. The ith FCE hasinput b_(i)[n_(t)]=c_(i)[n_(t)] and frequency step size Δ_(i)=K_(i)Δ,whereK _(2i-1) =K _(2i)=2^(i−1) for i=1,2, . . . ,13, andK _(i)=2¹³ for i=27,28, . . . ,34.  (19)

The DEM encoder's input sequence, c[n_(t)], is obtained from the DCOinput sequence asc[n _(t)]=d[n _(t)]/Δ+2¹⁵+2¹³−1  (20)

As shown in FIG. 3, the DEM encoder 300 consists of 33 digital switchingblocks (SBs) 302, labeled S_(k,r) for k=1, 2, . . . , 16, and r=1, 2, .. . , 17, configured in a tree structure. The 13 shaded SBs are calledsegmenting SBs, whereas the other 20 SBs are called non-segmenting SBs.The functional details of the SBs are shown in FIGS. 4A-4C. The top andbottom outputs of each segmenting SB are½(c_(k,r)[n_(t)]−1−s_(k,1)[n_(t)]) and 1+s_(k,1)[n_(t)], respectively,where c_(k,1)[n_(t)] is the SB input sequence, and s_(k,1)[n_(t)],called a switching sequence, is 0 when c_(k,1)[n_(t)] is odd and ±1otherwise. Similarly, the top and bottom outputs of each non-segmentingSB are ½(c_(k,r)[n_(t)]−s_(k,r)[n_(t)]) and½(c_(k,r)[n_(t)]+s_(k,r)[n_(t)]), respectively, where c_(k,r)[n_(t)] isthe SB input sequence and s_(k,r)[n_(t)] is 0 when c_(k,r)[n_(t)] iseven and ±1 otherwise.

Regardless of the SB type, each switching sequence is zero-mean and hasa first-order highpass-shaped power spectral density (PSD) that peaks atf_(in)/2. It is generated in two's complement format by the logic shownin FIG. 4C, wherein d_(k,r)[n_(t)] is generated within each SB and iswell-modeled as a two-level white random sequence that takes on valuesof 0 and 1 with equal probability and is independent of thed_(k,r)[n_(t)] sequences in the other SBs.

Extension to Multi-Rate Segmented DEM

Now suppose that the smallest practical FCE frequency step size isΔ_(min)=2⁸Δ. As the lower 16 FCEs in the example above all havefrequency step sizes smaller than Δ_(min), the bottom 16 outputs of theDEM encoder can no longer drive FCEs directly. The preferred multi-rateDEM architecture 500 in the DCO control logic 501 shown in FIG. 5addresses this situation, where a bottom 4 FCEs make up a fractional FCEbank 502, the top 18 FCEs make up an integer FCE bank 504, andw_(t)=p_(t)−1 is a T_(fast)-delayed version of p_(t), whereT_(fast)=1/f_(fast). As in FIG. 1, n_(t)=g(p_(t)) changes synchronouslywith p_(t).

A slow DEM encoder 506 is a modified version of the DEM encoder in FIG.3. Its outputs c₁₇[n_(t)], c₁₈[n_(t)], . . . , c₃₄[n_(t)] are identicalto those in FIG. 3, and instead of outputs c₁[n_(t)], c₂[n_(t)], . . . ,c₁₆[n_(t)] it has an output, x_(f)[n_(t)], supplied to a second orderdigital ΔΣ modulator 508, given by

$\begin{matrix}{{x_{f}\lbrack n_{t} \rbrack} = {\Delta{\sum\limits_{i = 1}^{16}{{K_{i}( {{c_{i}\lbrack n_{t} \rbrack} - {1\text{/}2}} )}.}}}} & (21)\end{matrix}$

Each c_(i)[n_(t)] takes on values of 0 and 1, so (19) and (21) implythat |x_(f)[n_(t)]|≤255Δ and x_(f)[n_(t)] is restricted to multiples ofΔ.

The slow DEM encoder could be implemented from the DEM encoder of FIG. 3directly by combining c₁[n_(t)], c₂[n_(t)], . . . , c₁₆[n_(t)] as in(21), but the preferred structure of FIG. 6 provides a simpler and moreelegant approach. As implied by FIG. 4B, the sum of the outputs of eachnon-segmenting SB is equal to the SB's input, so it follows from (21),FIG. 3 and FIG. 4A that x_(f)[n_(t)] can be computed directly from thebottom outputs of S_(16,1), S_(15,1), . . . , S_(9,1) as

$\begin{matrix}{{x_{f}\lbrack n_{t} \rbrack} = {\Delta{\sum\limits_{k = 9}^{16}{2^{16 - k}{{s_{k,1}\lbrack n_{t} \rbrack}.}}}}} & (22)\end{matrix}$

Hence, as shown in FIG. 6, S_(1,1), S_(1,2), . . . , S_(1,8) are notnecessary in the slow DEM encoder 506.

The Δ scale factor shown in FIG. 6 is not an actual multiplier; it justdenotes that the subsequent digital logic should interpret the LSB ofx_(f)[n_(t)] to represent a DCO frequency step size of Δ.

As shown in FIG. 5, x_(f)[n_(t)] is sampled at a rate of f_(fast) by thesecond-order digital ΔΣ modulator 508, whose functional diagram is shownin FIG. 7. The dither sequence, d_(ΔΣ)[p_(t)], is generated such that itcan be well-modeled as a two-level white random sequence that isindependent of d[n_(t)] and x_(f)[n_(t)] and takes on values of 0 andΔwith equal probability. It ensures that the ΔΣ modulator's 508quantization noise is asymptotically independent of x_(f)[n_(t)] andd_(ΔΣ)[p_(t)], and has a PSD equal to that of the output of a filterwith transfer function (1−z⁻¹)² driven by white noise with a variance ofΔ_(min) ²/12. See, S. Pamarti, J. Welz, and I. Galton, “Statistics ofthe Quantization Noise in 1-Bit Dithered Single-Quantizer DigitalDelta-Sigma Modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.54, no. 3, pp. 492-503, March 2007. The ΔΣ modulator output is quantizedto values in the set {−2Δ_(min), −Δ_(min), 0, Δ_(min), 2Δ_(min)} and isgiven byy _(ΔΣ)[p _(t)]=x _(f)[n _(t)]+e _(ΔΣ)[p _(t)],  (23)where e_(ΔΣ)[p_(t)] is second-order highpass-shaped quantization noiseplus d_(ΔΣ)[p_(t)].

In FIG. 5, a fast DEM encoder 510 can be a conventional mismatch-shapingnon-segmented DEM encoder with a clock rate of f_(fast). It isimplemented as a tree of non-segmenting SBs, and it maps y_(ΔΣ)[p_(t)]to four 1-bit sequences, each of which drives an FCE with a frequencystep size of Δ_(min).

Each b_(i)[w_(t)] in FIG. 5, for i=1, 2, 3, 4, is clocked at a rate off_(fast) and toggles rapidly enough such that the FCE frequencytransitions from the fractional FCE bank introduce high-frequency errorcomponents to the DCO phase error. Such components are lowpass filteredby the DCO, so f_(fast) can be chosen so that they are not a problem inpractice. Consequently, the frequency transitions of the FCEs from thefractional FCE bank 502 are modeled as ideal, so that f_(i)(t) is givenby (11) for i=1, 2, 3, 4.

It follows thatf _(F)(t)=α_(F) y _(ΔΣ)[w _(t)]+e _(F)(t),  (24)where α_(F) is the average of α_(i) for i=1, 2, 3, 4 and e_(F)(t) is afunction of the errors introduced by the fractional FCE bank 502 and theswitching sequences from the fast DEM encoder 510. The fast DEM encoder510 ensures that e_(F)(t) is free of nonlinear distortion, uncorrelatedwith y_(ΔΣ)[w_(t)], and has a first-order highpass-shaped PSD that peaksat f_(fast)/2, so f_(fast) can be chosen so that this term is not aproblem in practice. Thus, substituting (23) into (24) and neglectinge_(F)(t) givesf _(F)(t)=α_(F) x _(f)[g(w _(t))]+α_(F) e _(ΔΣ)[w _(t)].  (25)

As shown in FIG. 5, the c₁₇[n_(t)], c₁₈[n_(t)], . . . , c₃₄[n_(t)]outputs of the slow DEM encoder 506 drive the same FCEs as those of theDEM encoder of FIG. 3. This implies that f_(I)(t) is given by

$\begin{matrix}{{{f_{I}(t)} = {{{\alpha_{I}(t)}{d\lbrack {g( w_{t} )} \rbrack}} + {{\gamma_{I}(t)}{d\lbrack {g( {w_{t} - 1} )} \rbrack}} + {e_{I}(t)}}},} & (26) \\{where} & \; \\{{{e_{I}(t)} = {\Delta{\sum\limits_{k,r}^{\;}\{ {{{\alpha_{k,r}(t)}{s_{k,r}\lbrack {g( w_{t} )} \rbrack}} + {{\gamma_{k,r}(t)}{s_{k,r}\lbrack {g( {w_{t} - 1} )} \rbrack}}} \}}}},} & (27)\end{matrix}$

α_(I)(t), γ_(I)(t), α_(k,r)(t) and γ_(k,r)(t) (defined in Appendix Abelow) are T_(fast)-periodic waveforms that depend on the errorsintroduced by the integer FCE bank 504, and the summation indicesindicate the summation over all k and r values corresponding to the SBswithin the slow DEM encoder 506.

The contribution to the DCO frequency from both FCE banks 502 and 504 isf_(tune)(t)=f_(I)(t)+f_(F)(t), so (25) and (26) imply thatf _(tune)(t)=α_(I)(t)d[g(w _(t))]+γ_(I)(t)d[g(w _(t)−1)]+α_(F) e _(ΔΣ)[w_(t)]+e _(M)(t),  (28)wheree _(M)(t)=e _(I)(t)+α_(F) x _(f)[g(w _(t))]  (29)is called FCE mismatch error. e_(M)(t) is a linear combination of theswitching sequences from the slow DEM encoder whose coefficients dependon the errors introduced by both FCE banks 502 and 504.

The γ_(I)(t)d[g(w_(t)−1)] term in (28) is proportional to aT_(fast)-delayed version of d[g(w_(t))], so it represents a linearfiltering operation. This term tends to be much smaller than the desiredsignal component, α_(I)(t)d[g(w_(t))], so it is not a problem inpractice. The α_(F)e_(ΔΣ)[w_(t)] term is proportional to ΔΣ quantizationnoise plus dither so it is free of nonlinear distortion, is uncorrelatedwith the other terms in (28), and has a highpass-shaped PSD. Thee_(M)(t) term also has these properties because it is a linearcombination of the switching sequences from the slow DEM encoder. ThePSD of α_(F)e_(ΔΣ)[w_(t)] peaks at f_(fast)/2, whereas the PSD ofe_(M)(t) peaks at f_(in)/2. Hence, f_(fast) can be increased to make theDCO phase error introduced by α_(F)e_(ΔΣ)[w_(t)] negligible, but thiswould not reduce the DCO phase error contribution from e_(M)(t).Therefore, e_(M)(t) is the only problematic term in (28).

Substituting (22) and (27) into (29) yields

$\begin{matrix}{{{e_{M}(t)} = {\Delta{\sum\limits_{k,r}^{\;}\{ {{\delta_{k,r}{s_{k,r}\lbrack {g( w_{t} )} \rbrack}} + {{\gamma_{k,r}(t)}( {{s_{k,r}\lbrack {g( {w_{t} - 1} )} \rbrack} - {s_{k,r}\lbrack {g( w_{t} )} \rbrack}} )}} \}}}},} & (30) \\{\mspace{79mu}{where}} & \; \\{\mspace{79mu}{\delta_{k,r} = \{ {\begin{matrix}{{{\alpha_{k,r}(t)} + {\gamma_{k,r}(t)} + {\alpha_{F}2^{16 - k}}},} & {{{{if}\mspace{14mu} k} \geq 9},{r = 1}} \\{{{\alpha_{k,r}(t)} + {\gamma_{k,r}(t)}},} & {otherwise}\end{matrix},} }} & (31)\end{matrix}$is constant for each k and r, even though neither α_(k,r)(t) norγ_(k,r)(t) are constant. The non-constant terms in each α_(k,r)(t) areequal in magnitude but opposite in sign to the corresponding terms inγ_(k,r)(t), so α_(k,r)(t)+γ_(k,r)(t), and hence δ_(k,r), are constant.Therefore, the terms proportional to δ_(k,r) in (30) represent the DCOfrequency error contribution from FCE static gain errors, whereas theterms proportional to γ_(k,r)(t) in (30) represent the DCO frequencyerror contribution from non-ideal FCE frequency transitions.

Adaptive FCE Mismatch Noise Cancellation

The purpose of the present MNC is to cancel most of the DCO phase errorthat would otherwise be caused by e_(M)(t). To do this, the sequence

$\begin{matrix}{{{e_{MNC}\lbrack p_{t} \rbrack} = {\Delta{\sum\limits_{k,r}^{\;}\{ {{\alpha_{k,r}{s_{k,r}\lbrack n_{t} \rbrack}} + {b_{k,r}( {{s_{k,r}\lbrack {g( w_{t} )} \rbrack} - {s_{k,r}\lbrack n_{t} \rbrack}} )}} \}}}},} & (32)\end{matrix}$where a_(k,r) and b_(k,r) are called the MNC coefficients, is injectedinto the fractional path of the multi-rate DEM encoder. The ideal MNCcoefficient values, i.e., the values of a_(k,r) and b_(k,r) for whichthe DCO phase error contribution of e_(M)(t) is minimized, are estimatedwith a least-mean-square (LMS)-like algorithm. The algorithm is similarto a conventional LMS algorithm in the sense that it consists of a setof coefficients that are updated over time based on how strongly knownsignals are correlated to an error measurement.

We next explain how e_(MNC)[p_(t)] affects the DCO's phase error, howthe FCE mismatch error is measured, and how the MNC coefficients areadaptively computed from the FCE mismatch error measurement.

MNC Sequence Application

FIG. 8 shows the fractional path of the multi-rate DEM encoder shown inFIG. 5 modified to accommodate MNC. The e_(MNC)[p_(t)] sequence(determined by FIGS. 11A-11C, discussed below) is subtracted fromx_(f)[n_(t)] prior to the ΔΣ modulator, and the output range of the ΔΣmodulator 508, the range of the fast DEM encoder 510, and the number ofFCEs of the FCE bank 502 driven by the fast DEM encoder 510 are all fourtimes those of the original FIG. 5 system to accommodate the resultingdynamic range increase. Thus, f_(F)(t) is still given by (24), but nowγ_(ΔΣ)[p_(t)] is given by the right side of (23) minus e_(MNC)[p_(t)].Despite having the same qualitative properties as before, α_(F) ande_(F)(t) in (24) are slightly different in the modified system becauseof the additional FCEs.

An analysis shows that f_(time)(t) is now given byf _(tune)(t)=α_(I)(t)d[g(w _(t))]+γ_(I)(t)d[g(w _(t)−1)]+α_(F) e _(ΔΣ)[w_(t)]+e _(R)(t),  (33)wheree _(R)(t)=e _(M)(t)−α_(F) e _(MNC)[w _(t)]  (34)is the residual FCE mismatch error, i.e., what is left of e_(M)(t) whene_(MNC)[p_(t)] is applied. It follows from (30), (32) and (34) that

$\begin{matrix}{{{e_{R}(t)} = {\Delta{\sum\limits_{k,r}^{\;}\{ {{\delta_{k,{r - {res}}}{s_{k,r}\lbrack {g( w_{t} )} \rbrack}} + {{\gamma_{k,{r - {res}}}(t)}( {{s_{k,r}\lbrack {g( {w_{t} - 1} )} \rbrack} - {s_{k,r}\lbrack {g( w_{t} )} \rbrack}} )}} \}}}},} & (35)\end{matrix}$respectively.

Given that δ_(k,r) is constant, there exists an a_(k,r) that causesδ_(k,r-res)=0. In contrast, there is no b_(k,r) that causesγ_(k,r-res)(t) to vanish completely, because γ_(k,r)(t) is not constant.However, γ_(k,r)(t) is T_(fast)-periodic so there exists a b_(k,r) thatmakes the DC component of γ_(k,r-res)(t) zero, such that γ_(k,r-res)(t)is a linear combination of sinusoids with frequencies that are non-zeromultiples of f_(fast). Therefore, it follows from Error! Referencesource not found. that if

$\begin{matrix}{{a_{k,r} = {{\frac{\delta_{k,r}}{\alpha_{F}}\mspace{14mu}{and}\mspace{14mu} b_{k,r}} = {\frac{1}{\alpha_{F}T_{fast}}{\int_{0}^{T_{fast}}{{\gamma_{k,r}(\tau)}d\;\tau}}}}},} & (36)\end{matrix}$for each k and r, thenδ_(k,r-res)=0 and ∫₀ ^(T) ^(fast) γ_(k,r-res)(τ)dτ=0.  (37)

In the absence of FCE static mismatches, a_(k,r)=0, and if the FCEfrequency transitions are ideal, b_(k,r)=0.

Phase error is the integral of frequency error, so the DCO phase errorintroduced by e_(R)(t) is given byθ_(R)(t)=∫₀ ^(t) e _(R)(τ)dτ.  (38)

If (37) is satisfied, then (35) and (38) imply that

$\begin{matrix}{{{\theta_{R}(t)} = {\Delta{\sum\limits_{k,r}^{\;}{( {{s_{k,r}\lbrack {g( {w_{t} - 1} )} \rbrack} - {s_{k,r}\lbrack {g( w_{t} )} \rbrack}} ){\int_{0}^{t - {p_{t}T_{fast}}}{{\gamma_{k,{r - {res}}}(u)}{du}}}}}}},} & (39)\end{matrix}$where t−p_(t)T_(fast)=t−└f_(fast)t┘T_(fast)<T_(fast). The term withinthe parenthesis in (39) equals zero when g(w_(t))−g(w_(t)−1)=0 ands_(k,r)[g(w_(t))−1] −s_(k,r)[g(w_(t))] otherwise. Given thatg(w_(t))−g(w_(t)−1) can only take on values from the set {0, 1}, thens _(k,r)[g(w _(t)−1)]−s _(k,r)[g(w _(t))]=(g(w _(t))−g(w _(t)−1))(s_(k,r)[g(w _(t))−1]−s _(k,r)[g(w _(t))]).  (40)

Furthermore, g(w_(t)) is a T_(fast)-delayed version of n_(t), whichincreases by one unit every T_(in)=1/f_(in), so g(w_(t))−g(w_(t)−1) isT_(in)-periodic and is given by

$\begin{matrix}{{{g( w_{t} )} = {{g( {w_{t} - 1} )} = {\sum\limits_{k = {- \infty}}^{\infty}{r( {t - {kT}_{i\; n}} )}}}},} & (41)\end{matrix}$where r(t)=1 for t∈[T_(fast), 2T_(fast)) and 0 otherwise. It followsfrom (41) that the Fourier expansion of g(w_(t))−g(w_(t)−1) is

$\begin{matrix}{\frac{f_{i\; n}}{f_{fast}} + {\sum\limits_{m = 1}^{\infty}{\frac{2}{m\;\pi}{\sin( {m\;\pi\frac{f_{i\; n}}{f_{fast}}} )}{{\cos( {2\pi\;{{mf}_{i\; n}\lbrack {t - {\frac{3}{2}T_{fast}}} \rbrack}} )}.}}}} & (42)\end{matrix}$

Thus, if the conditions shown in (37) are satisfied, (39), (40) and (42)imply that θ_(R)(t) would be given by second-order shaped noisemultiplied by a T_(in)-periodic waveform and a DC-free T_(fast)-periodicwaveform. Consequently, e_(R)(t) would introduce components withfrequencies around f_(n,m)=nf_(fast)±mf_(in) to the DCO's phase error,where n=1, 2, 3, . . . and m=0, 1, 2, . . . . It follows from (42) thatthe power of the components around frequencies f_(n,m) with m nearmultiples of f_(fast)/f_(in) is very low. Therefore, θ_(R)(t) would notbe a problem if f_(fast) is large enough because e_(R)(t) would onlyintroduce high-frequency components to the DCO's phase error that wouldbe lowpass filtered by the DCO. Simulation results also suggest thatθ_(R)(t) is not a problem provided the conditions shown in (37) aresatisfied and f_(fast) is large enough.

FCE Mismatch Error Measurement

The ideal MNC coefficient values are estimated as part of a feedbackloop in a digital fractional-N PLL that incorporates the DCO. This isdone during the PLL's normal operation by adaptively adjusting a_(k,r)and b_(k,r) such that the conditions shown in (37) are satisfied foreach k and r, thereby minimizing e_(R)(t).

The purpose of a fractional-N PLL is to generate a periodic outputsignal, v_(PLL)(t), with frequency f_(PLL)=(N+α)f_(ref), where N is apositive integer, α is a fractional value and f_(ref) is the frequencyof a reference oscillator waveform, v_(ref)(t). The general form of adigital fractional-N PLL without MNC is shown in FIG. 9. It consists ofa phase-error-to-digital converter (PEDC) 902, a lowpass digital loopfilter (DLF) 904, and a DCO 906. The PEDC's 902 output is anf_(ref)-rate digital sequence of the formp[n]=−θ_(PLL)[n]+e _(p)[n],  (43)where θ_(PLL)[n] is an estimate of the PLL's phase error and e_(p)[n] isadditive error that includes quantization error from the PEDC's 902digitization process as well as error from circuit noise and othernon-ideal circuit behavior in both the PEDC and reference oscillator.

A modified version of the DCO 906 contains the preferred multi-rate DEMstructure of FIG. 5 with the MNC correction of FIG. 8 withf_(in)=f_(ref). Typically, f_(fast)-clk is a divided-down version ofv_(PLL)(t). Given that f_(PLL)=(N+α)f_(ref), f_(ref) and f_(fast) areincommensurate frequencies when α≠0, it is not possible for n_(t) tochange synchronously with p_(t)=└f_(fast)t┘ if n_(t)=└f_(ref)t┘.Therefore, as shown in FIGS. 10A & 10B, in practice the DCO input issynchronized to f_(fast)-clk so (4) is satisfied, i.e., so n_(t) onlychanges at times μ_(n), which are multiples of T_(fast), instead oftimes nT_(ref), where T_(ref)=1/f_(ref) is the reference period. It iscommon practice in digital PLLs to synchronize the DLF 904 output to theclock signal of the fractional path, so this is not a specialrequirement of the proposed system. A conventional circuit to avoidmetastability issues is also needed as part of the synchronizationcircuit shown in FIG. 10A, but it has been omitted for simplicity.

A requirement of a PLL is to suppress low-frequency DCO error, which isachieved by subjecting additive frequency error introduced by the DCO toa highpass filter that has at least one zero at DC. In the following,the impulse response of this filter is denoted as h[n], and its runningsum, i.e., h[0]+h[1]+ . . . +h[n], is denoted as l[n]. p[n] can bewritten asp[n]=p _(ideal)[n]+p _(R)[n],  (44)

where p_(ideal)[n] represents the contribution to p[n] of all noisesources except FCE mismatches and p_(R)[n] is the contribution to p[n]from e_(R)(t). Specifically, p_(R)[n] (with references to definitions inAppendix B) is given by

$\begin{matrix}{{{p_{R}\lbrack n\rbrack} = {{\Delta\alpha}_{F}T_{fast}{\sum\limits_{i = 0}^{n - 1}{\sum\limits_{k,r}^{\;}{\{ {{y_{k,{r - a}}\lbrack i\rbrack} + {y_{k,{r - b}}\lbrack i\rbrack}} \}{l\lbrack {n - 1 - i} \rbrack}}}}}},} & (45)\end{matrix}$where y_(k,r-a)[t]+y_(k,r-b)[i] is proportional to the PLL's frequencyerror introduced by the s_(k,r)[n] sequences. If a_(k,r) and b_(k,r) in(32) are replaced by a_(k,r)[n_(t)] and b_(k,r)[n_(t)], respectively,theny _(k,r-a)[i]=(q _(i−1)−3)s _(k,r)[i−1]a _(k,r-error)[i−1]+3s _(k,r)[i]a_(k,r-error)[i]  (46)anda _(k,r-b)[i]=(s _(k,r)[i−1]−s _(k,r)[i])b _(k,r-error)[i],  (47)

where q_(i−1) is the number of T_(fast) periods between times μ_(i−1)and μ_(i), anda _(k,r-error)[n]=a _(k,r)[n]−a _(k,r) and b _(k,r-error)[n]=b_(k,r)[n]−b _(k,r)   (48)are the MNC coefficient errors at sample time n.

The term proportional to s_(k,r)[i] in (46) arises because the time atwhich the PEDC 902 samples the PLL's phase error, which is given byμ_(n)+4T_(fast) in the design example, is not equal to the time at whichthe integer FCE bank's inputs are updated, i.e., μ_(n)+T_(fast).Accordingly, the integer FCE bank's inputs are updated three T_(fast)before the PLL's phase error is sampled, which causes y_(k,r-a)[i] todepend on s_(k,r)[i−1] and also on s_(k,r)[i].

As implied by (44)-(47), the PEDC's 902 output has information regardingthe MNC coefficient errors. The MNC coefficient estimation processdescribed next is based on this result and on the properties of theswitching sequences.

MNC Coefficients Estimation

A digital fractional-N PLL with the multi-rate DEM encoder and MNCtechnique is shown in FIG. 11A. The details of MNC logic 1102 are shownin FIG. 11B and FIG. 11C, wherein

$\begin{matrix}{{t_{k,r}\lbrack n\rbrack} = {\sum\limits_{i = 0}^{n}{s_{k,r}\lbrack i\rbrack}}} & (49)\end{matrix}$is the running sum of s_(k,r)[n], and K_(a) and K_(b) are called the MNCgains. The MNC logic block consists of an adder and 25 s_(k,r)[n_(t)]residue estimators 1104.

It follows from FIG. 4 that each s_(k,r)[n] sequence is a concatenationof sequences of the form 1, 0, . . . , 0, −1, 0, . . . , 0 or −1, 0, . .. , 0, 1, 0, . . . , 0, where each 0 is present only when the input ofthe s_(k,r)[n] generator is zero. Thus, |s_(k,r)[n]|≤1, |t_(k,r)[n]|≤1and |s_(k,r)[n]−s_(k,r)[n−1]|≤2 for all n, so the multipliers in FIG.11(c) are simple in terms of hardware.

The s_(k,r)[n_(t)] residue estimators 1104 are responsible for thecomputation of the MNC coefficients. At each sample time, the MNCcoefficient errors are measured and a_(k,r)[n_(t)] and b_(k,r)[n_(t)]are updated such that they approach the values shown in (36). Themeasurement of the MNC coefficient errors is based on the statisticalproperties of the switching sequences.

Although each s_(k,r)[n] sequence depends on the input of itscorresponding SB, when it is non-zero, its sign depends on d_(k,r)[n].Given that the d_(k,r)[n] sequences are independent of the d_(k,r)[n]sequences in the other SBs, this provides enough randomization for thes_(k,r)[n] sequences to be uncorrelated with each other. Furthermore, asthe d_(k,r)[n] sequences are also independent of all electronic devicenoise sources in the PLL, each s_(k,r)[n] sequence is uncorrelated withall such sources as well, and it is also uncorrelated with the PEDC's902 quantization noise in PLLs where such noise source is uncorrelatedwith the PLL's phase error.

Hence, in such cases, the s_(k,r)[n] sequences are uncorrelated with allPLL noise except the terms in p[n] arising from e_(R)(t), i.e.,p_(R)[n].

The y_(k,r-a)[i] and y_(k,r-b)[i] terms in p[n] depend on the MNCcoefficient errors, and such terms are proportional to functions of thes_(k,r)[n] sequences. Specifically, it can be seen from (44)-(47) thatp[n] has information about an accumulated version of(q _(n−2)−3)s _(k,r)[n−2]a _(k,r-error)[n−2],  (50)and that p[n]−p[n−1] has information about(s _(k,r)[n−2]s _(k,r)[n−1])b _(k,r-error)[n−1].  (51)

Therefore, it follows that the accumulator inputs in FIG. 11C, i.e.,−p[n]t_(k,r)[n−2] and (p[n−1]−p[n])(s_(k,r)[n−2]−s_(k,r)[n−1]), whennon-zero, are noisy estimates of a_(k,r-error)[n] and b_(k,r-error)[n],respectively, so they can be used to adaptively compute the ideal MNCcoefficients. In practice, the top and bottom branches within eachs_(k,r)[n_(t)] residue estimator 1104 interfere with each other in a waythat makes the accumulator inputs have information about both MNCcoefficient errors. However, extensive simulations indicate that the MNCcoefficient values converge to their ideal values regardless of suchinterferences provided the MNC gains are set properly to avoidinstability in the feedback loops.

It would also be possible to correlate p[n−1]−p[n] by s_(k,r)[n−2] toget an estimate of a_(k,r-error)[n]. However, as a_(k,r)[n] is onlyupdated when the accumulator input is non-zero, correlating p[n−1]−p[n]against s_(k,r)[n−2] instead of −p[n] against t_(k,r)[n−2] wouldsignificantly decrease the convergence speed of a_(k,r)[n] becausenormally s_(k,r)[n−2] is zero more often than t_(k,r)[n−2]. Althoughcorrelating −p[n] against t_(k,r)[n−2] effectively increases the errorvariance of a_(k,r)[n], as explained next, this problem can be mitigatedby reducing K_(a).

As is common in most LMS-like algorithms, the choice of K_(a) and K_(b)represents a tradeoff. The larger the MNC gains, the faster theconvergence, but the larger the error variance of a_(k,r)[n] andb_(k,r)[n]. Also, as the s_(k,r)[n_(t)] residue estimators comprise twoLMS-like loops in parallel that interfere with each other, K_(a) andK_(b) each affect the convergence time and error variance of botha_(k,r)[n] and b_(k,r)[n]. Although it might be possible to developclosed-form expressions that quantify these tradeoffs, the authorscurrently use simulations to assist the design process and to choose thevalues of K_(a) and K_(b).

Simulation Results

The multi-rate DEM and the MNC methods of the preferred embodimentsdescribed above were tested in an event-driven behavioral simulation ofa modified version of the ΔΣ frequency-to-digital converter basedfractional-N PLL presented in [C. Weltin-Wu, G. Zhao, and I. Galton, “AHighly-Digital Frequency Synthesizer Using Ring-OscillatorFrequency-to-Digital Conversion and Noise Cancellation,” IEEEInternational Solid-State Circuits Conf., pp. 1-3, February 2015; C.Weltin-Wu, G. Zhao, and I. Galton, “A 3.5 GHz Digital Fractional-NFrequency Synthesizer Based on Ring Oscillator Frequency-to-DigitalConversion,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp.2988-3002, December 2015]. As explained in [C. Weltin-Wu, E. Familier,and I. Galton, “A Linearized Model for the Design of Fractional-N PLLsbased on Dual-Mode Ring Oscillator FDCs,”IEEE Trans. Circuits Syst. I,Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], p[n] is givenby (43) where e_(p)[n] is first-order shaped quantization noise that isuncorrelated with the PLL's phase error plus error from both the PEDCand reference oscillator.

The DLF consists of two single-pole IIR stages and aproportional-integral stage. Its transfer function is

$\begin{matrix}{{{L(z)} = {{K_{M}( {K_{P} + \frac{K_{I}}{1 - z^{- 1}}} )}{\prod\limits_{i = 0}^{1}\frac{\lambda_{i}}{1 - {( {1 - \lambda_{i}} )z^{- 1}}}}}},} & (52)\end{matrix}$where K_(M), K_(P), K_(I), λ₀ and λ₁ are constant loop filterparameters. The DCO consists of an LC oscillator core with apower-of-two-weighted coarse capacitor bank, an integer FCE bank 502 anda fractional FCE bank 504 in accordance with FIG. 5. The latter two aredriven by the multi-rate DEM encoder 500 shown in FIG. 5 and modified asshown in FIG. 8 with f_(fast)=f_(PLL)/8 and Δ_(min)=40 kHz (i.e.,Δ=156.25 Hz).

The static gain error of the ith FCE was modeled as an additivezero-mean Gaussian random variable with a standard deviation of 5% ofΔ_(i) divided by the square root of Δ_(i)/Δ_(min). The FCE frequencytransitions were modeled as second-order transients that settle withinone T_(fast) period. The parameters of these transients, such as thedamping factor and the natural frequency, are modelled as randomvariables with means and standard deviations determined fromtransistor-level simulation results. FIG. 12 shows example frequencytransients used in the simulation.

The simulated noise parameters of the DCO and the reference oscillator,as well as the PEDC internal parameters were f_(ref)=26 MHz, N=134 andα=0.0003846153, so that f_(PLL)=3.484 GHz and f_(fast)=435.5 MHz. TheDLF parameters used were K_(M)=1.25, K_(P)=2⁴, K_(I)=2⁻⁴, λ₀=2⁻³ andλ₁=2⁻², and the MNC gains were set to K_(a)=2⁻³ and K_(b)=2⁻⁵. Thesimulated PLL has a bandwidth of 206 kHz and a phase margin of 63degrees.

FIG. 13A shows the simulated PLL phase noise PSD with the multi-rate DEMtechnique disabled, i.e., with the flip-flops in both the slow and fastDEM encoders frozen. The two curves in FIG. 13A were obtained from twodifferent simulations: one in which d_(I)[n_(t)] is constant and anotherone in which d_(I)[n_(t)] changes frequently. Although the DCO inputsequence does not vary significantly in the short term once the PLL islocked, its moving average drifts over time such that d_(I)[n_(t)]eventually begins to change frequently, at which point it degrades thePLL's phase noise as shown in FIG. 13A. Once the multi-rate DEMtechnique is enabled, whether or not d_(I)[n_(t)] changes has nosignificant effect on the DCO's frequency, so spectral breathing nolonger occurs.

FIG. 13B shows the simulated PLL phase noise PSD with the multi-rate DEMtechnique enabled for two cases: one case with just static gain errors,and the other case with just non-ideal frequency transitions. FIG. 13Cshows the simulated PLL phase noise PSD considering both sources oferror with the multi-rate DEM technique enabled and with the MNCtechnique disabled and enabled. The theoretical PLL phase noise PSD forideal FCEs, which was computed using the linearized model presented in[C. Weltin-Wu, E. Familier, and I. Galton, “A Linearized Model for theDesign of Fractional-N PLLs based on Dual-Mode Ring OscillatorFDCs,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp.2013-2023, August 2015], is also plotted as the dashed curves in FIGS.13A-13C to provide a comparison baseline.

As shown in FIG. 13A, when the MNC technique is enabled the resultingphase noise PSD matches the theoretically-predicted phase noise PSD forideal FCEs after 13·10⁷ reference periods (5 seconds) from a cold start.This implies a phase noise improvement of more than 20 dB at an offsetfrequency around 10 MHz. As the FCE mismatches are mostly determined bycircuit component mismatches, they are not expected to changesignificantly over time. Hence, once obtained, the MNC coefficients canbe stored in memory and used subsequently by the PLL, thereby avoidingfuture convergence time delays.

FIG. 14 shows the evolution of the MNC coefficient errors over time fromthe simulation used to generate the curves in FIG. 13C. As shown in FIG.14, some b_(k,r)[n] coefficients initially move away from their idealvalues. As explained above, this happens because the top and bottombranches of each s_(k,r)[n_(t)] residue estimator interfere with eachother so that the error estimate at the input of each accumulator isbiased by the MNC coefficient error of the opposite branch. If the MNCgains are set as in FIGS. 14A and 14B, this is not a problem becausethis effect becomes less significant as either one or both MNCcoefficients approach their ideal values.

It follows from (46) and (47) that the terms proportional toa_(k,r-error)[n] in p[n] are q_(n)−3 times larger than thoseproportional to b_(k,r-error)[n] (e.g., q_(n)≅16 in the design example),so for K_(a)=K_(b), the error variance of each b_(k,r)[n] is expected tobe larger than that of a_(k,r)[n]. Therefore, in order to make the errorvariance of the b_(k,r)[n] coefficients comparable to that of thea_(k,r)[n] coefficients, K_(b) has to be smaller than K_(a). As shown inFIGS. 14A & 14B, this causes the b_(k,r)[n] coefficients to converge totheir ideal values at a slower rate than the a_(k,r)[n] coefficients, sothe convergence speed of the MNC technique is limited by K_(b).Nonetheless, it follows from FIGS. 14A & 14B that the a_(k,r)[n]coefficients get close to their ideal values in less than 10⁷ referenceperiods (˜0.4 seconds). Hence, as the most significant sources of phasenoise are the FCE static gain errors, the MNC method allows for aconsiderable phase noise improvement in less than half a second.

To reduce the cold-start convergence time of the MNC technique, largeMNC gains can be used initially and decreased over time. See, W. Y. Chenand R. A. Haddad, “A Variable Step Size LMS Algorithm,” Proc. 33^(rd)Midwest Symp. Circuits and Systems, pp. 423-426, August 1990. FIGS. 15Aand 15B shows the evolution of the MNC coefficient errors over time for7.8.10⁷ reference periods (3 seconds) for an example case in which K_(a)and K_(b) are initially set to 2⁻¹ and 2⁻², respectively, and thendivided by two at the times indicated by the vertical dashed lines. Inthis case, the MNC coefficients reach the final values shown in FIGS.14A & 14B in roughly 3 seconds, and the a_(k,r)[n] coefficients getclose to their ideal values in less than 2·10⁶ reference periods (˜0.08seconds), which is five times faster than in FIGS. 14A & 14B.

Appendix A

It follows from FIG. 5 and (17) that

$\begin{matrix}{{f_{I}(t)} = {\sum\limits_{i = 5}^{22}{\lbrack {{( {{b_{i}\lbrack w_{t} \rbrack} - {1\text{/}2}} ){\alpha_{i}(t)}\Delta_{i}} + {( {{b_{i}\lbrack {w_{t} - 1} \rbrack} - {1\text{/}2}} ){\gamma_{i}(t)}}} \rbrack.}}} & (53)\end{matrix}$

Expressions for each b_(i)[w_(t)]=c_(i+12)[g(w_(t))] in terms ofd[g(w_(t))] and the switching sequences can be found by tracing throughthe tree of FIG. 6 and applying (20) and the expressions shown in FIG.4(a) and FIG. 4(b). This leads to

$\begin{matrix}{{{{c_{i}\lbrack {g( w_{t} )} \rbrack} - {1\text{/}2}} = {{m_{i}{d\lbrack {g( w_{t} )} \rbrack}\text{/}\Delta} + {\sum\limits_{k,r}^{\;}{\kappa_{k,r,i}{s_{k,r}\lbrack {g( w_{t} )} \rbrack}}}}},} & (54)\end{matrix}$wherem _(i)=0 for 17≤i≤26 and m _(i)=2⁻¹⁶ for 27≤i≤34,  (55)and each x_(k,r,i) is one of 0, −½, ½, 2^(−k) or 2^(−k). Combining(4)(19) and (53)-(55) yields (26) and (27), where α_(I)(t) and γ_(I)(t)are the averages of α_(i)(t) and (2⁻¹³/Δ)γ_(i)(t) for i=15, 16, . . . ,22, respectively,

$\begin{matrix}{{\alpha_{k,r}(t)} = {{\sum\limits_{i = 5}^{22}{{\alpha_{i}(t)}K_{i + 12}\kappa_{k,r,{i + 12}}\mspace{14mu}{and}\mspace{14mu}{\gamma_{k,r}(t)}}} = {\sum\limits_{i = 5}^{22}{\frac{\gamma_{i}(t)}{\Delta}{\kappa_{k,r,{i + 12}}.}}}}} & (56)\end{matrix}$

Each α_(I)(t), γ_(I)(t), α_(k,r)(t) and γ_(k,r)(t) is T_(fast)-periodic,because it is a linear combination of α_(I)(t) and γ_(i)(t), which areT_(fast)-periodic.

Appendix B

The phase error of the digital PLL shown of FIG. 9 is given byθ_(PLL)(t)=∫₀ ^(t) ψv _(PLL)(u)du,  (57)where ψ_(PLL)(t) is the PLL's frequency error at time t. The θ_(PLL)[n]term in (43) is a sampled version of θ_(PLL)(t) given byθ_(PLL)[n]=θ_(PLL)(τ_(n)),  (58)where τ_(n)=nT_(ref)+ and λ_(n) is a small implementation-dependentdeviation of τ_(n) from its ideal value. It follows from (43), (57) and(58) that

$\begin{matrix}{{{p\lbrack n\rbrack} = {{p\lbrack 0\rbrack} - {T_{ref}{\sum\limits_{i = 1}^{n}{\psi_{PLL}\lbrack i\rbrack}}} + {e_{p}\lbrack n\rbrack}}},} & (59)\end{matrix}$where

$\begin{matrix}{{\psi_{PLL}\lbrack i\rbrack} = {\frac{1}{T_{ref}}{\int_{\tau_{i - 1}}^{\tau_{i}}{{\psi_{PLL}(u)}{du}}}}} & (60)\end{matrix}$is the PLL's average frequency error over the time interval [τ_(i−1),τ_(i)] and p[0] is the initial value of p[n]. FIG. 9 and (60) imply thate_(R)(t) causes a term in ψ_(PLL)[i] given by

$\begin{matrix}{{{\{ {e_{R}*h} \}\lbrack i\rbrack} = {\sum\limits_{j = 0}^{\infty}{{h\lbrack j\rbrack}{e_{R}\lbrack {i - j} \rbrack}}}},} & (61) \\{where} & \; \\{{e_{R}\lbrack i\rbrack} = {\frac{1}{T_{ref}}{\int_{\tau_{i - 1}}^{\tau_{i}}{{e_{R}(u)}{du}}}}} & (62)\end{matrix}$and h[j] is the impulse response of the highpass filtering operationimposed by the PLL on the DCO's additive frequency error as discussed inthe description above.

In the design example of the example embodimentλ_(n)=4.2T_(fast)+⅛T_(fast)v[n], where v[n] is an integer-valuedsequence restricted to the set {−6, 5, . . . , 5, 6}, soτ_(n)=nT_(ref)+4.2T_(fast)+⅛T_(fast)v[n]. As the magnitude of⅛T_(fast)v[n] is at most ¾T_(fast), its effect is negligible.Furthermore, for the sake of simplicity, τ_(n) is assumed to be given byτ_(n)=μ_(n)+4T _(fast),  (63)where μ_(n), as shown FIG. 10B, is a multiple of T_(fast). Given that0<μ_(n)−nT_(ref)≤T_(fast) for all n and that T_(fast) is a smallfraction of T_(ref), this approximation does not significantly affectthe following results. Substituting Error! Reference source not found.with a_(k,r) and b_(k,r) replaced by a_(k,r)[g(w_(t))] andb_(k,r)[g(w_(t))], respectively, into (35), and the result of thisoperation and (63) into (62) yields

$\begin{matrix}{{e_{R}\lbrack i\rbrack} = {\frac{\Delta}{T_{ref}}{\int_{\mu_{i - 1} + {4T_{fast}}}^{\mu_{i} + {4T_{fast}}}{\{ {{( {\delta_{k,r} - {\alpha_{F}{a_{k,r}\lbrack {g( w_{t} )} \rbrack}}} ){s_{k,r}\lbrack {g( w_{t} )} \rbrack}} + {( {{\gamma_{k,r}(t)} - {\alpha_{F}{b_{k,r}\lbrack {g( w_{t} )} \rbrack}}} )( {{s_{k,r}\lbrack {g( {w_{t} - 1} )} \rbrack} - {s_{k,r}\lbrack {g( w_{t} )} \rbrack}} )}} \}{{dt}.}}}}} & (64)\end{matrix}$

Given that t∈[μ_(n), μ_(n+1)) implies g(p_(t))=n−1, it follows thatg(w_(t))=i−2 for t∈[μ_(i−1)+T_(fast), μ_(i)+T_(fast)) and g(w_(t))=i−1for t∈[μ_(i)+T_(fast), μ_(i)+T_(fast)), so (64) can be written as

$\begin{matrix}{{{e_{R}\lbrack i\rbrack} = {{- \Delta}\frac{\alpha_{F}T_{fast}}{T_{ref}}{\sum\limits_{k,r}^{\;}\{ {{\gamma_{k,{r - a}}\lbrack {i - 1} \rbrack} + {y_{k,{r - b}}\lbrack {i - 1} \rbrack}} \}}}},} & (65)\end{matrix}$where y_(k,r-a)[i] and y_(k,r-b)[i] are given by (46) and (47),respectively, and it has been assumed thatq_(i)=(μ_(i+1)−μ_(i))/T_(fast) is greater than 3 for all i (e.g.,q_(i)≅16 in the design example). Substituting (65) into (61) and theresult into (59), rearranging terms and considering that s_(k,r)[n]=0for n<0 gives (44) and (45)

While specific embodiments of the present invention have been shown anddescribed, it should be understood that other modifications,substitutions and alternatives are apparent to one of ordinary skill inthe art. Such modifications, substitutions and alternatives can be madewithout departing from the spirit and scope of the invention, whichshould be determined from the appended claims.

Various features of the invention are set forth in the appended claims.

The invention claimed is:
 1. A digital fractional-N phase locked loop(PLL) with multi-rate dynamic element matching (DEM) and an adaptivemismatch-noise cancellation (MNC), comprising: a phase error to digitalconverter; a digital loop filter to suppress quantization noise of thephase error to digital converter and drive a digitally controlledoscillator; a digitally controlled oscillator (DCO) with a multi-rateDEM encoder driving an integer bank of frequency control elements and afractional bank of frequency control elements; and adaptivemismatch-noise cancellation logic operating to cancel DCO phase errorarising from frequency control element (FCE) static and dynamic mismatcherror by estimating ideal MNC coefficient values during PLL normaloperation, estimating MNC coefficient errors at each sample time, andupdating the MNC coefficient values to approach zero FCE static anddynamic mismatch error.
 2. The digital fractional-N phase locked loop ofclaim 1, wherein the updating of the MNC coefficient values is conductedonce for each time the phase error of the PLL is measured.
 3. Thedigital fractional-N phase locked loop of claim 1, wherein themulti-rate DEM comprises: a slow DEM encoder that drives the integerbank of frequency control elements and a second order ΔΣ modulator; anda fractional path, wherein the fractional path includes the second-orderdigital ΔΣ modulator driving a fast DEM encoder that drives thefractional bank of frequency control elements, wherein the second-orderdigital ΔΣ modulator and fast DEM encoder are clocked at a higherfrequency compared to that of the slow DEM encoder.
 4. The digitalfractional-N phase locked loop of claim 3, wherein the ΔΣ modulator'squantization noise is asymptotically independent of its input and dithersequences used in the ΔΣ modulator.
 5. The digital fractional-N phaselocked loop of claim 3, wherein the adaptive mismatch-noise cancellationlogic injects an MNC correction sequence, which is computed from the MNCcoefficient values and the switching sequences generated inside the slowDEM encoder, into the fractional path.
 6. The digital fractional-N phaselocked loop of claim 3, wherein the adaptive mismatch-noise cancellationlogic estimates the ideal MNC coefficients with a least-mean-square(LMS)-like algorithm.
 7. The digital fractional-N phase locked loop ofclaim 3, wherein the adaptive mismatch-noise cancellation logicestimates the ideal MNC coefficients based on the statistical propertiesof switching sequences generated inside the slow DEM encoder.